The present invention relates to a driving circuit, a semiconductor device including the same, and a control method of the driving circuit, and relates to, for example, a driving circuit, a semiconductor device including the same, and a control method of the driving circuit suitable for improving the reliability without increasing the power consumption.
In general, a word line driver for driving a word line of a memory cell array is configured using a CMOS gate that is excellent in a high-speed operation and low power consumption.
Here, in the case where a word line of a DRAM (Dynamic Random Access Memory), a non-volatile memory, or the like is driven, a word line driver needs to apply a voltage as high as possible to the word line in order to accurately read data stored in a memory cell. Accordingly, in the case where the word line of the DRAM, the non-volatile memory, or the like is driven, the word line driver applies a high voltage to the word line by being driven by a power supply voltage higher than a rated voltage.
However, in the word line driver configured using the CMOS gate, a high voltage is steadily applied to a plurality of specific MOS transistors, and thus these MOS transistors possibly suffer dielectric breakdown. Accordingly, there has been a problem that the reliability of a semiconductor device in which the word line driver is mounted is deteriorated.
A solution to such a problem is disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713. A driver disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713 includes an output-stage inverter, a first inverter that is driven by a high voltage VDH to output the inverted signal of an input signal Vin to the gate of a PMOS transistor provided in the output-stage inverter, and a second inverter that is driven by a low voltage VDL (<high voltage VDH) to output the inverted signal of the input signal Vin to the gate of an NMOS transistor provided in the output-stage inverter.
Here, since the second inverter is driven by the low voltage VDL, a high voltage is not steadily applied to each MOS transistor configuring the second inverter. Therefore, the possibility that each MOS transistor configuring the second inverter suffers dielectric breakdown is low. Accordingly, the reliability of the driver disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-163713 can be improved because the number of MOS transistors suffering dielectric breakdown can be reduced.